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Google doubles down on TPU 8th-gen line with 8tx and 8i Max

TPU 8i Max doubles compute, SRAM, and HBM over TPU 8i in the same rack footprint.

Google on November 9 added two specialized chips to its eighth-generation Tensor Processing Unit family: TPU 8tx for secure, confidential inference and TPU 8i Max for high-density, long-context workloads1,3. The chips are set to launch in 20274.

The expansion brings the eighth-generation TPU lineup to four systems in a single year, following TPU 8t for large-scale training and TPU 8i for real-time reasoning, both introduced at Google Cloud Next '26 in April.

TPU 8i Max is a dual-chip package targeting massive context windows. Google said it delivers double the compute, double the SRAM, and double the high-bandwidth memory of TPU 8i, while fitting twice the silicon into the same rack footprint — reducing floor space and power consumption per unit of work in data centers.

TPU 8tx is designed for government agencies and companies in regulated industries that need hardware-level protection for sensitive data during inference2. The chip is to be paired with AMD CPUs.

Google's Tensor Processing Units have primarily served internal products such as Search, YouTube, and Gemini, but the company has been making them available through its cloud business to attract enterprise AI customers. TPU sales made a meaningful contribution to results in the September quarter, according to Alphabet, with Google Cloud revenue more than doubling to $30.71 billion. Alphabet shares were up more than 3 percent in early trading on November 9.

Bloomberg News first reported the new chips earlier on November 9. Google said it is also making TPUs more accessible by supporting PyTorch, open-source software, and automated tools for developers.

The 4 articles this piece was written from — of 6 independent outlets covering the story.

ANALYSIS Splitting the eighth-generation line into four task-specific variants — training, reasoning, confidential inference, and high-density long-context — marks a shift from general-purpose accelerator design toward workload-matched silicon, a strategy that ties hardware selection directly to the stage of the AI lifecycle a customer is operating in.

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